1. Field of the Invention
The present invention relates to a nonvolatile memory cell and a method of fabricating a nonvolatile semiconductor memory including the memory cell.
2. Description of the Related Art
Memory cells storing charge on both sides of a gate electrode have recently been proposed for use in nonvolatile semiconductor memory devices. Japanese Patent Application Publications No. 2005-64295 and 2004-342927, for example, propose memory cells with the general structure illustrated in FIG. 1. This memory cell 220 is essentially a field-effect transistor with a source area 234 and a drain area 236 formed in a well 212 in a semiconductor substrate 201, which is insulated by a gate insulation film 222 from a polysilicon layer 224 and tungsten silicide layer 225 that constitute a gate electrode 226. The channel area 228 below the gate electrode 226 is flanked by a pair of variable resistance areas 230, 232. Over them is formed a silicon oxide layer 238 and a silicon nitride layer 239 constituting a charge storage body 240 that also lines the sides of the gate electrode 226. A pair of sidewalls 242 complete the structure. The memory cell operates as follows.
When information is written in the charge storage body 240 near the drain area 236, for example, if the charge storage body 240 initially has no stored charge (the ‘erased’ state), the source area 234 is placed at the ground voltage level, a positive voltage is applied to the drain area 236, and a positive voltage is applied to the gate electrode 226. Hot electrons generated in variable resistance area 232 are selectively injected into the charge storage body 240 near the drain area 236, thereby ‘programming’ this charge storage body 240.
When information is read from the charge storage body 240 near the drain area 236, the drain area 236 is placed at the ground voltage level, a positive voltage is applied to the source area 234, and a positive voltage is applied to the gate electrode 226. If this charge storage body 240 has been programmed and stores charge, the electric field of the stored charge increases the resistance of variable resistance area 232, making it difficult to supply carriers to the channel area 228, and current flow is suppressed. If the charge storage body 240 is in the erased state, that is, if no charge is stored, then the resistance of variable resistance area 232 is not increased, an adequate number of carriers is supplied to the channel area 228, and adequate current flows. The value of the information (‘0’ or ‘1’) is determined from the difference in current between the erased and programmed states.
Information is written into and read from the charge storage body 240 near the source area 234 by similar procedures with the source and drain voltages reversed.
Japanese Patent Application Publication No. 2004-342927 discusses advantageous structures of the source and drain areas with particular attention to specific impurity concentrations.
Since the reading of information relies on the difference in current between the erased and programmed states, if this current difference is small, it becomes difficult to distinguish between ‘0’ and ‘1’ information. Even in the nonvolatile semiconductor memories described in Japanese Patent Application Publication No. 2004-342927, means for ensuring an adequate current difference were lacking.